1. Field of the Invention
The present invention is related to the field of peak detection.
2. Background Art
Peak detectors are devices for determining the maximum (peak) amplitude of an input signal. Such circuits typically comprise a holding capacitor for storing charge from the input signal and control circuitry to govern application of the input signal to the holding capacitor. Thus, the control circuit controls charging and discharging of the holding capacitor. In conjunction with the control circuit, the holding capacitor is charged up to store a voltage that increases toward the peak value of the input signal.
FIG. 1 is a diagram illustrating a prior art peak detector comprising NPN transistor Q102 anti holding capacitor C102. Supply voltage V.sub.CC is provided to the collector of transistor Q102. Input signal 100 is coupled to the base of transistor Q102. The emitter of transistor Q102 is coupled to an external holding (memory) capacitor C102 through input pad IP102. The second terminal of capacitor C102 is coupled to ground. The output voltage V.sub.OUT is taken across capacitor C102 with respect to ground. The circuit illustrated in FIG. 1 is an open-loop peak detector.
In FIG. 1, when input signal 100 becomes more positive than the sum of output voltage V.sub.OUT across capacitor C102 and the base-emitter voltage V.sub.BE of transistor Q102, the emitter of transistor Q102 is pulled up. Transistor Q102 sources current to holding capacitor C102. This current charges up capacitor C102 until the input signal 100 decreases below the instantaneous value of output voltage V.sub.OUT plus the base-emitter voltage V.sub.BE of transistor Q102. When the input signal 100 provided to the base of transistor Q102 drops below this level, the emitter-base junction of transistor Q102 is reverse biased. In this state, current is not conducted through transistor Q102 to capacitance C102. Thus, capacitor C102 holds the most positive value of the input signal 100 less the V.sub.BE drop of transistor Q102 that capacitor C102 charged to.
A disadvantage of this prior art circuit is that the output voltage cannot reach the peak amplitude of the input signal. The output voltage V.sub.OUT stored on capacitor C102 has a maximum voltage level of one base-emitter voltage drop less than the peak input signal 100. Also, the base-emitter voltage drop of transistor Q102 makes the prior art peak detector insensitive to peaks of the input signal 100 less than approximately 0.6 volts above the instantaneous voltage level of the output signal V.sub.OUT.
Another disadvantage of this prior art circuit is inaccuracy in the output voltage due to variations in base-emitter voltage of the transistor. The variations in base-emitter voltage of transistor Q102 are caused by temperature and current variations. Thus, the offset of the peak voltage across capacitor C102, due to the base-emitter voltage of transistor Q102, varies over temperature and device beta.
FIG. 2 is a diagram illustrating another prior art peak detector. This closed-loop peak detector comprises an operational amplifier OP202, diode D202 and holding capacitor C102. Input signal 100 is coupled to the non-inverting input of operational amplifier OP202. The output of operational amplifier OP202 is coupled to a first terminal of diode D202. The second terminal of diode D202 is coupled to a first terminal of capacitor C102 and to the inverting input of operational amplifier OP202. The second terminal of capacitor C102 is coupled to ground. The output voltage V.sub.OUT is provided across capacitor C102.
Input signal 100 drives operational amplifier OP202. In turn, operational amplifier OP202 controls holding (memory) capacitor C102 through diode D202. The close-loop feedback of output voltage V.sub.OUT to operational amplifier OP202 causes operational amplifier OP202 to provide a voltage at its output that is one diode drop above output voltage V.sub.OUT. The operational amplifier OP202 acts as a unity gain buffer that can only source current due to diode D202. When input signal 100 drops below output voltage V.sub.OUT, diode D202 is reverse-biased so that no charging current is provided to capacitor C102.
When input signal 100 exceeds the output voltage V.sub.OUT, operational amplifier OP202 generates a voltage to forward bias diode D202. With diode D202 forward biased, operational amplifier OP202 sources a current to charge capacitor C102. The charging current increases the output voltage V.sub.OUT across capacitor C102 until it matches the input signal 100. The closed-loop of this prior art circuit interrupts the charging current through diode D202 when the instantaneous output voltage V.sub.OUT equals the input signal 100. In this prior art circuit, the effect of the offset voltage of diode D202 is reduced. However, this prior art peak detector has several disadvantages.
A disadvantage of the prior art is due to the finite slew-rate of the operational amplifier in the peak detector. The voltage output of operational amplifier OP202 goes into negative saturation when the input signal is lower than the output voltage V .sub.OUT. The finite slew-rate prevents the voltage generated by operational amplifier OP202 from accurately following higher frequency input signals 100 when input signal 100 exceeds the output voltage V.sub.OUT.
Another disadvantage of the prior art is "droop" of the output voltage due to bias and leakage currents. The input bias current of operational amplifier OP202 discharges capacitor C102 producing a decrease in output voltage V.sub.OUT. Similarly, the leakage current of diode D202 also produces droop in the output voltage V.sub.OUT.
Yet another disadvantage of the prior art is poor noise rejection due to the diode. Transients in input signal 100 that exceed the instantaneous value of output voltage V.sub.OUT force diode D202 to conduct. This produces an error in the output voltage because the charging current sourced by operational amplifier OP202 increases the output voltage V.sub.OUT. Thus, the prior art provides poor rejection of noise.